In clock or data recovery and in other phase and timing control operations, phase or timing adjustments are usually performed after a phase or timing error is detected. Traditionally, a Phase Locked Loop (PLL) is employed, in which the frequency of a Voltage Controlled Oscillator (VCO) is adjusted to achieve the phase adjustment or alignment through a number of cycles. The amount of the phase change is the integral of the difference between the VCO frequency and the reference frequency. These are generally analog PLL circuits which contain various lumped capacitors and lumped resistors to form the analogue low pass filter function for obtaining a smoothed or filtered control signal for VCO. Monolithic circuit integration of the PLL along with large scale digital circuitry is difficult, especially using standard manufacturing processes for digital circuits. In addition, problems associated with phase locked loop design such as susceptibility to digital switching noise limits the traditional CMOS analog PLL design to applications, at less than 100 MHZ.
In digital data recovery or digital signal synchronization applications, digitally controlled delay cell technologies are often utilized. A plurality of such delay cells can be cascaded to form a delay line which can then delay a signal, whether data, clock or control signal, to provide a plurality of delayed, or phase shifted copies of the original signal from the taps of the delay line. These delayed signals can then be sampled, or detected, or registered to be analyzed in subsequent logic to determine their phase relationship with a reference signal or signals to enable signal synchronization, data recovery and other tasks. Prior art tapped delay lines are known which can provide phase shifted copies of a signal, but the delay line or the taps of the delay line are not regulated or calibrated. In one such prior arrangement described in U.S. Pat. No. 4,821,297, a locally generated reference clock running at the data rate frequency is delayed or phase shifted by an N-length tapped delay to provide N copies of the clock with phase step of .DELTA..PHI. between each adjacent tap. The phase adjustment step size of the resolution is determined by the delay amount per tap and the total phase shift is determined by N times the phase step. Since no delay time regulation is provided, the total phase shift is not a constant and depends on various manufacturing processes or operating conditions if it is implemented in a monolithic integrated circuit format. Even if the clock reference frequency is known so that the delay line can be designed to be long enough to ensure all possible phases, problems arise when there is a frequency difference between the data frequency or the remote transmitter clock and the local receiver clock. If the data frequency is slightly lower than the locally generated reference clock frequency, the phase decision circuit will detect this slow phase drift and inform the delay path selector to increment the delay. This process will continue as long as the data keeps arriving. Theoretically, the delay line has to be infinitely long to provide a constant phase increment in the same direction. Accordingly, a need exists to have a method and apparatus which can handle the above problem, and which provides a phase shift of equal increments or decrements for unlimited number of cycles.
In the simultaneously filed related application, "All Digital High Speed Algorithmic Data Recovery Scheme and Apparatus using Locally Generated Compensated Broad Band Time Ruler and Data Edge Position Averaging," AMD Docket Number A895, Ser. No. 8/021924 filed Feb. 24, 1993, the locally generated time ruler used as the bit rate recovered clock is constantly phase compared with the averaged data transition positions, and is phase shifted by an up/down control signal produced in a edge distribution sampler and phase adjust decision circuit. In the event that a constant frequency difference exists between the incoming data and the locally generated time ruler clock, a slow process takes place to adjust the phase relation of the clock leading edge to follow the slow "drifting" of the center of the data bit (known as the center of the data eye) in relation to the local time ruler signal. A range of delay is needed which provides tapped outputs for all possible phases in the given resolution determined by the delay of the delay cell, and which is calibrated to shift 360 degree of the locally generated timing signal such that the signal from the last tap of the calibrated range has the same phase as that from the first tap.